1. Field of the Invention
The present invention relates generally to the preparation and writing of data from the memory of a computer to a storage medium. More specifically, the invention relates to a method and circuit of determining the adjust bit of write data to be recorded on a recording medium by a pulse width modulation (PWM) system.
2. Description of the Related Art
Recently, there has been an increasing demand for higher recording densities on recording media like magneto-optical disks. Instead of the conventional PPM (Pit Position Modulation) system, the PWM system has been receiving a great deal of attention these days as a method of recording data on a recording medium with a high density.
As a method of recording data on a recording medium, the PWM system is superior to the PWM system in improving the recording density. The PWM system records data in such a manner that the sum of the DC levels become zero or a value close to zero so as to ensure the accurate reading of data. The sum of the total of the widths of the regions in one recording block where a “1” (a positive value) is to be recorded plus the total of the widths of the regions in that recording block where a “0” (a negative value) is to be recorded, should equal zero. That is, the total of the widths of the regions where a “1” is to be recorded is equal to the total of the widths of the regions where a “0” is to be recorded.
Generally, each sector on a recording medium has an ID section and a data section. As what is recorded in the ID section is predetermined, the adjustment required to make the sum of the DC levels zero (“bit adjustment”) can be easily determined. Since data from a user (“user data”) to be recorded in the data section is not fixed, bit adjustment should be performed as needed. FIG. 1 schematically shows the recording format in a data section 80 after RLL (Run-Length Limited) code conversion. The bit adjustment in this data section 80 is carried out by rewriting an adjust bit area (“adjust bit”) 81a consisting of one bit in each of a plurality of resync pattern areas 81 in the data section 80.
FIG. 2 shows the block circuit of a conventional adjust-bit determining circuit 50 which determines the value of the adjust bit 81a.
User data, which is always one-byte data, is input to an encoder 51, which converts the user data to 12 channel bits based on a predetermined RLL code, more particularly, an RLL (1, 7) code, and outputs the resultant data to first and second adjust-bit inserting circuits 52 and 53. This conversion is executed using a conversion table which is incorporated in the encoder 51.
The first and second adjust-bit inserting circuits 52 and 53 sequentially receive the same user data which has been converted to channel bits by the encoder 51. Then, those adjust-bit inserting circuits 52 and 53 add previously-prepared resync pattern data to this user data and output the resultant data to first and second modulators 54 and 55, respectively. The adjust-bit inserting circuits 52 and 53 affix an adjust bit value to be recorded in the adjust bit 81a of the resync pattern area 81. The adjust bit value to be affixed to the user data by the first adjust-bit inserting circuit 52 differs from the adjust bit value to be affixed to the user data by the second adjust-bit inserting circuit 53.
More specifically, the adjust bit value which the first adjust-bit inserting circuit 52 affixes to the user data is “1” while the adjust bit value which the second adjust-bit inserting circuit 53 affixes to the user data is “0”. The adjust-bit inserting circuits 52 and 53 convert data of resync patterns to be affixed to user data, based on the aforementioned RLL (1, 7) code.
The first modulator 54 modulates data in the data section 80 (user data, each resync pattern where the adjust bit is “1” and so forth) which has been converted to RLL (1, 7) codes. That is, the first modulator 54 modulates individual pieces of data, converted to RLL (1, 7) codes, to the PWM format from the PPM format and outputs each piece of modulated data to a first up/down counter 56. The second modulator 55 modulates data in the data section 80 (user data, each resync pattern where the adjust bit is “0” and so forth) which has been converted to RLL (1, 7) codes. That is, the second modulator 55 modulates individual pieces of data, converted to RLL (1, 7) codes, to accomplish modulation conversion from PPM to PWM, and outputs each piece of modulated data to a second up/down counter 57.
The first and second up/down counters 56 and 57 sample the data from the first and second modulators 54 and 55 with a predetermined sampling frequency and add “1” to the count values when the sampled values have a high level (logical value of “1”). When the sampled values have a low level (logical value of “0”), the up/down counters 56 and 57 subtract “1” from the count values. That is, each of the first and second up/down counters 56 and 57 acquires the sum of the high and low DC levels. The computation to acquire this sum is generally called Digital Sum Value (DSV) computation.
The first up/down counter 56 samples the PWM data from the first modulator 54, and performs DSV computation. The second up/down counter 57 does likewise for the second modulator 55.
The first and second up/down counters 56 and 57 perform this DSV computation from the head data in the data section 80 (data in a third VFO area 82) on up to immediately before the adjust bit 81a of the second resync pattern area 81. When DSV computation by both counters 56 and 57 is completed, these counters 56 and 57 output count values N1 and N2 to a comparator 58. The comparator 58 compares the count value N1 of the first up/down counter 56 with the count value N2 of the second up/down counter 57.
When the count value N1 is smaller than the count value N2, the comparator 58 outputs a select signal Z to make the adjust bit value “1”. Recording a “1” in the adjust bit 81a of the first resync pattern area 81 causes the sum of the DC levels to be closer to zero than recording a “0” in the adjust bit 81a of the first resync pattern area 81.
On the other hand, when the count value N2 is smaller than the count value N1 the comparator 58 outputs a select signal Z to make the adjust bit value “0”. Recording a “0” in the adjust bit 81a of the first resync pattern area 81 causes the sum of the DC levels to be closer to zero than recording a “1” in the adjust bit 81a of the first resync pattern area 81.
When DSV computation on up to just before the adjust bit 81a of the third resync pattern area 81 is completed, both counters 56 and 57 output count values N1 and N2 up to that point of time to the comparator 58. The comparator 58 compares both values with each other and outputs the select signal Z for the adjust bit 81a of the previous resync pattern area, i.e., the second resync pattern area 81.
Thereafter, the value of the adjust bit 81a provided in each resync pattern area 81 of the data section 80 is likewise determined. Accordingly, data is recorded on an optical disk in such a way that the sum of the DC levels becomes zero or a value close to zero.
The adjust-bit determining circuit requires two groups of circuits for DSV computation: the circuits 52, 54 and 56 for performing DSV computation based on data having a “1” previously recorded in the adjust bit 81a, and the circuits 53, 55 and 57 for performing DSV computation based on data having a “0” previously recorded in the adjust bit 81a. This structure for an adjust-bit determining circuit is large in scale, and results in increased consumed power and cost.
Further, the encoder 51 converts input user data to an output data length which is 1.5 times greater than the input data in order to convert the user data to RLL (1, 7) codes. The encoder 51 therefore must output data to the adjust-bit inserting circuits 52 and 53 at a faster rate than the rate of the input user data. That is, the adjust-bit inserting circuits 52 and 53, the modulators 54 and 55 and the counters 56 and 57 must operate at a clock having a 1.5 times higher frequency. The consumed power of the adjust-bit determining circuit therefore increases because of the higher operation frequency.
Accordingly, it is desirable to reduce the consumed power and the circuit scale of an apparatus which records data in this PWM system.